The present invention relates to a phase locked loop (PLL) including a voltage controlled oscillator (VCO) circuit, and more particularly to techniques which are effectively applied to incorporation of a loop filter on a PLL into a semiconductor chip. More specifically, the present invention relates to techniques which are effectively utilized for a transmission PLL loop in a high frequency semiconductor circuit, for example, used in radio communication devices such as a portable telephone for modulating and upconverting a transmission signal.
A radio communication device (mobile communication device) represented by a portable telephone typically comprises a semiconductor integrated circuit (generally referred to as a high frequency IC) which has functions of upconverting and modulating a transmission signal, downconverting and demodulating a received signal, and the like; a semiconductor integrated circuit (baseband IC) which has functions of converting a transmission signal to I, Q signals, and recovering reception data from demodulated I, Q signals; an electronic part referred to as a power module which contains a high frequency power amplifier, an associated bias circuit, an impedance matching circuit, and the like; and an electronic part referred to as a front end module which contains a transmission/reception switching circuit, a low pass filter, an impedance matching circuit and the like.
In radio communication devices, with the recent trend of reducing the number of parts for a smaller size and a lower cost of the devices, conscious efforts have been made to incorporate as many circuits as possible into a single or several semiconductor integrated circuits. One of such efforts includes an attempt to provide a semiconductor chip with a built-in loop filter disposed on a loop of a transmission PLL within a high frequency IC.
Generally, a second-order filter FLT as illustrated in FIG. 1 has been used for the loop filter for a transmission PLL within a high frequency IC for providing a loop band characteristic required thereto. A charge pump is generally indicated by CP. FIG. 2 is a graph showing the frequency characteristic of the filter FLT in FIG. 1, which has zero at frequency f1 and a pole at frequency f2. The frequency f1 and the frequency f2 in the illustrated loop filter are expressed by the following equations:f1=1/{2π·C1·R}f2=(C1+C2)/2π·C1·C2·R  (1)
Such a second-order filter employs two capacitive elements, wherein a loop filter for a transmission PLL handles relatively high frequencies, causing the larger capacitive element C1 to have a high capacitive value on the order of nF (nanofarad), which makes it difficult to integrate the capacitive element C1 itself on a chip. Thus, an external element is often used for the capacitive element C1 to make up the loop filter.
On the other hand, in order to reduce the capacitance values of capacitive elements used in a second-order loop filter, a technique has been developed and proposed for providing each capacitive element with a charge pump disposed in front thereof for charging and discharging the capacitive element, for example, as illustrated in FIG. 3 (see, for example, 0018-9200/02 IEEE “A Fully Integrated CMOS Frequency Synthesizer With Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless System”).